Digital electronic circuits are subject to special levels of radiation exposure, particularly when used in the aerospace industry, in high-energy physics and in nuclear medicine. Ionizing radiation causes changes in the channel conductivity of a MOS transistor, due to the influence of positively charged holes trapped in lateral dielectric isolation layers, such as shallow trench isolation (STI) layers or local oxidation of silicon (LOCOS) layers. This effect is called the total ionizing dose (TID) effect. The TID effect thus causes undesired, greatly increased leakage currents between the source and drain of MOS transistors that are exposed to ionizing radiation.
The use of enclosed layout transistors (ELT) to prevent TID effects is known from the prior art. A ring-shaped design of the MOS gate separating the source and drain from each other prevents changes in the channel conductivity of MOS transistors due to TID effects. One disadvantage of enclosed layout MOS transistors, however, is that it is not possible to implement minimal gate widths that are otherwise technologically feasible. The structure of such transistors is also highly asymmetric, with large differences in the source and drain areas. As a final point, such transistor structures take up significantly more area compared to a transistor arrangement with a linear MOS transistor layout.